SH7713 datasheet(662/904 Pages) RENESAS

662 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 622 of 860

REJ09B0288-0150

• FIFO transmit request: TDREQ (transmit interrupt source)

• FIFO receive request: RDREQ (receive interrupt source)

The request conditions for FIFO transmit or receive can be specified individually. The request

conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and

RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 17.8 and 17.9 summarize the conditions

specified by SIFCTR.

Table 17.8

Conditions to Issue Transmit Request

TFWM2 to TFWM0

Number of

Requested Stages

Transmit Request

Used Areas

000

Empty area is 16 stages

100

Empty area is 12 stages or more

101

Empty area is 8 stages or more

110

Empty area is 4 stages or more

Smallest

111

Empty area is 1 stage or more

Largest

Table 17.9

Conditions to Issue Receive Request

RFWM2 to RFWM0

Number of

Requested Stages

Receive Request

Used Areas

000

Valid data is 1 stage or more

100

Valid data is 4 stages or more

101

Valid data is 8 stages or more

110

Valid data is 12 stages or more

Smallest

111

Valid data is 16 stages

Largest

The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the

above stage number. Accordingly, an overrun error or underrun error occurs if data area or empty

area exceeds sixteen FIFO stages. FIFO transmission or reception request is cancelled when the

above condition is not satisfied even if the FIFO is not empty or full.

Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by

the following register.

• Transmit FIFO: The number of empty FIFO stages are indicated by the TFUA4 to TFUA0 bits

in SIFCTR.

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