SH7713 datasheet(658/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 618 of 860

REJ09B0288-0150

Figure 17.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.

24 23

16 15

8 7

24 23

16 15

8 7

24 23

16 15

8 7

24 23

16 15

8 7

Lch.data

Rch.data

(a) 16-bit stereo data

Data

(b) 16-bit monaural data

(d) 16-bit stereo data (left and right same audio output) data

Figure 17.5 Transmit/Receive Data Bit Alignment

Note:

In the figure, only the shaded areas are transmitted or received as valid data. Data in

unshaded areas is not transmitted or received.

Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.

Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.

To achieve left and right same audio output while stereo is specified for the transmit data, specify

the TLREP bit in SITDAR. Tables 17.5 and 17.6 show the audio mode specification for transmit

data and that for receive data, respectively. To execute 8-bit monaural transmission or reception,

use the left channel.

SH7713 Datasheet(PDF) 658 Page - Renesas Technology Corp