SH7713 datasheet(661/904 Pages) RENESAS

661 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 621 of 860

REJ09B0288-0150

Control by Secondary FS (Slave Mode 2): The CODEC normally outputs SIOFSYNC as

synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the

control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to

transmit or receive control data. This method is valid for SIOF slave mode. The following

summarizes the control data interface procedure by secondary FS.

• Transmit normal transmit data of LSB = 0 (The SIOF forcibly clears 0)

• To execute control data transmission, send transmit data of LSB = 1 (The SIOF forcibly set to

1 by writing SITCR)

• The CODEC outputs the secondary FS.

• The SIOF transmits control data (data specified by SITCR) or receives control data (stores in

SIRCR) synchronously with the secondary FT.

Figure 17.8 shows an example of control data interface timing by secondary FS.

SCK_SIO

RXD_SIO

TXD_SIO

SIOFSYNC

Lch.DATA

Setting: TRMD = 01,

TDLE = 1,

RDLE = 1,

CD0E = 1,

REDG = 0,

TDLA3 to TDLA0 = 0000,

RDLA3 to RDLA0 = 0000,

CD0A3 to CD0A0 = 0000,

FL = 1110 (Frame length: 128 bits),

TDRE = 0,

RDRE =0,

CD1E = 0,

TDRA3 to TDRA0 = 0000,

RDRA3 to RDRA0 = 0000,

CD1A3 to CD1A0 = 0000

LSB = 1 (Secondary FS request)

1 frame

1/2 frame

Normal FS

Secondary FS

Control

channel 0

Slot

No.0

Slot

No.0

Figure 17.8 Control Data Interface (Secondary FS)

17.4.6

FIFO

Overview: The transmit and receive FIFOs of the SIOF have the following features.

• Sixteen-stage 32-bit FIFOs for transmission and reception

• The FIFO pointer can be modified in one read or write cycle regardless of access size of the

CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)

• Regardless of access size, the number of access cycles is always two cycles of the P-bus cycle.

Transfer Request: The SIOF indicates a transfer request of the FIFO in the following two bits of

SISTR.

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