SH7713 datasheet(665/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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665 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 625 of 860

REJ09B0288-0150

Start

Yes

End

No.

Set SIMDR, SISCR, SITDAR,

SIRDAR, SICDAR, and SIFCTR

Set SCKE bit in SICTR to 1

Start SCK_SIO clock transmission

Set FSE bit in SICTR to 1

Set RXE bit in SICTR to 1

RDREQ=1?

Receive

ended?

Clear RXE bit in SICTR to 0

Set operating mode, serial clock,

slot positions for transmit/receive

data, slot position for control data,

and the upper limit value of FIFO

request

Set operation start for baud rate

generator

Set the start for frame

synchronous signal

Transmit frame

synchronous signal

Set to enable reception

Transmit serial clock

Time Chart

SIOF Settings

SIOF Operation

Submit reception request

according to the receive

FIFO threshold value

Reception

End reception

Read receive data

Set to disable reception

Read SIRDR

Store receive data from RXD_SIO

in SIRDR synchronously with SIOFSYNC

Figure 17.10 Example of Reception Operation in Master Mode

Transmission in Slave Mode: Figure 17.11 shows an example of settings and operation for slave

mode transmission.

SH7713 Datasheet(PDF) 665 Page - Renesas Technology Corp

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