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SH7713 Datasheet(PDF) 663 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 663 Page - Renesas Technology Corp |
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663 / 904 page ![]() Section 17 Serial I/O with FIFO (SIOF) Rev.1.50 Aug. 30, 2006 Page 623 of 860 REJ09B0288-0150 • Receive FIFO: The number of valid data stages that can be transferred by the CPU or DMAC are indicated by the RFUA4 to RFUA0 bits in SIFCTR. The above contents show the number of data which CPU or DMAC can transfer. 17.4.7 Transmission and Reception Procedures Transmission in Master Mode: Figure 17.9 shows an example of settings and operation for master mode transmission. |
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