SH7713 datasheet(660/904 Pages) RENESAS

660 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 620 of 860

REJ09B0288-0150

Table 17.7

Setting for Number of Control Data Channels

Bit

Number of Channels

CD0E

CD1E

17.4.5

Control Data Interface

Control data performs control command output to the CODEC and status input from the CODEC.

The SIOF supports the following two control data interface methods.

• Control by slot position

• Control by secondary FS

Control data is valid only when slot length is specified as 16 bits and MSB-first

transmission/reception is selected.

Control by Slot Position (Master Mode 1): Control data is transferred for all frames transmitted

or received by the SIOF by specifying the slot position of control data. This method can be used in

both SIOF master and slave modes. Figure 17.7 shows an example of control data interface timing

by slot position control.

Note:

When using this control method, use PCLK as the master clock (master clock selection

(MSSEL) = 1).

SCK_SIO

RXD_SIO

TXD_SIO

SIOFSYNC

Lch.DATA

Rch.DATA

Setting: TRMD = 00 or 10,

TDLE = 1,

RDLE = 1,

CD0E = 1,

REDG = 0,

TDLA3 to TDLA0 = 0000,

RDLA3 to RDLA0 = 0000,

CD0A3 to CD0A0 = 0001,

FL = 1110 (Frame length: 128 bits),

TDRE = 1,

RDRE = 1,

CD1E = 1,

TDRA3 to TDRA0 = 0010,

RDRA3 to RDRA0 = 0010,

CD1A3 to CD1A0 = 0011

Control

channel 0

Control

channel 0

1 frame

Slot No.0

Slot No.1

Slot No.2

Slot No.3

Figure 17.7 Control Data Interface (Slot Position)

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