SH7713 datasheet(668/904 Pages) RENESAS

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Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 628 of 860

REJ09B0288-0150

Table 17.10 shows the details of initialization upon transmission or reception reset.

Table 17.10 Transmission and Reception Reset

Type

Objects Initialized

Transmission reset

SITDR

Transmit FIFO write pointer, transmit FIFO read pointer

TCRDY bit, TFEMP bit, TDREQ bit in SISTR

TXE bit in SICTR

Reception reset

SIRDR

Receive FIFO write pointer, receive FIFO read pointer

RCRDY bit, RFFUL bit, RDREQ bit in SISTR

RXE bit in SICTR

Module Stop: In the module stop state, the SIOF stops transmit/receive operation with contents of

all registers retained. If transmit/receive operation is not performed immediately after the module

stop state is cleared, issue a transmit/receive reset.

17.4.8

Interrupts

The SIOF has four types of interrupts listed below. This classification is reflected to the IRR7

(SIOF0) and IRR8 (SIOF1) of the interrupt controller (INTC).

• Transmit interrupt (TXI)

• Receive interrupt (RXI)

• Control interrupt (CCI)

• Error interrupt (ERI)

Interrupt Sources: Interrupts can each be issued by several sources. Each source is shown as an

SIOF status in SISTR. Table 17.11 lists the SIOF interrupt sources.

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