SH7713 datasheet(672/904 Pages) RENESAS

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Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 632 of 860

REJ09B0288-0150

SCK_SIO

RXD_SIO

TXD_SIO

SIOFSYNC

Lch.DATA

TRMD = 00 or 10,

TDLE = 1,

RDLE = 1,

CD0E = 0,

REDG = 0,

TDLA3 to TDLA0 = 0000,

RDLA3 to RDLA0 = 0000,

CD0A3 to CD0A0 = 0000,

FL = 1101 (frame length: 64 bits)

TDRE = 0,

RDRE = 0,

CD1E = 0,

TDRA3 to TDRA0 = 0000,

RDRA3 to RDRA0 = 0000,

CD1A3 to CD1A0 = 0000

Slot No.0

Slot No.1

Slot No.2

Slot No.3

Setting:

1 frame

No bit delay

Figure 17.15 Transmission and Reception Timings (16-Bit Monaural Data (1))

16-bit Stereo Data (1): L/R method, rising edge sampling, slot No.0 used for left channel data,

slot No.1 used for right channel data, frame length = 32 bits

SCK_SIO

RXD_SIO

TXD_SIO

SIOFSYNC

Lch.DATA

TRMD = 11,

TDLE = 1,

RDLE = 1,

CD0E = 0,

REDG = 1,

TDLA3 to TDLA0 = 0000,

RDLA3 to RDLA0 = 0000,

CD0A3 to CD0A0 = 0000,

FL = 1100 (frame length: 32 bits)

TDRE = 1,

RDRE = 1,

CD1E = 0,

TDRA3 to TDRA0 = 0001,

RDRA3 to RDRA0 = 0001,

CD1A3 to CD1A0 = 0000

Rch.DATA

Slot No.0

Slot No.1

Setting:

1 frame

No bit delay

Figure 17.16 Transmission and Reception Timings (16-Bit Stereo Data (1))

16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left channel transmit

data, slot No.1 used for left channel receive data, slot No.2 used for right channel transmit data,

slot No.3 used for right channel receive data, frame length = 64 bits

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