 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7713 Datasheet(PDF) 655 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7713 Datasheet(HTML) 655 Page - Renesas Technology Corp |
|
|
655 / 904 page  Section 17 Serial I/O with FIFO (SIOF) Rev.1.50 Aug. 30, 2006 Page 615 of 860 REJ09B0288-0150 (a) Synchronous pulse 1 frame First bit data (MSB) 1 frame 1/2 frame length No delay 1-bit delay 1/2 frame length (b) L/R SCK_SIO SIOFSYNC TXD_SIO RXD_SIO SCK_SIO SIOFSYNC TXD_SIO RXD_SIO First bit of left channel data (MSB) First bit of right channel data (MSB) Figure 17.3 Serial Data Synchronization Timing Transmit/Receive Timing: The TXD_SIO transmission timing and RXD_SIO reception timing relative to the SCK_SIO signal can be set as the sampling timing in the following two ways. The transmit/receive timing is set using the REDG bit in SIMDR. In slave mode 1 and slave mode 2, only falling-edge sampling is available. • Falling-edge sampling • Rising-edge sampling Figure 17.4 shows the transmit/receive timing. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
