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SH7713 Datasheet(PDF) 652 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 652 Page - Renesas Technology Corp

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Section 17 Serial I/O with FIFO (SIOF)
Rev.1.50 Aug. 30, 2006 Page 612 of 860
REJ09B0288-0150
17.3.13
Serial Receive Control Data Register (SIRCR)
SIRCR is used to store the SIOF receive control data. SIRCR can be specified only when the FL3
to FL0 bits in SIMDR are specified as 1xxx. SIRCR is initialized by a power-on reset, software
reset, or receive reset.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 16
SIRC015 to
SIRC00
All 0
R
Control Channel 0 Receive Data
Store data received from the RXD_SIO pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmission or reception frame is
specified by the CD0A bit in SICDAR.
These bits are valid only when the CD0E bit in SICDAR
is set to 1.
15 to 0
SIRC115 to
SIRC10
All 0
R
Control Channel 1 Receive Data
Store data received from the RXD_SIO pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmission or reception frame is
specified by the CD1A bit in SICDAR.
These bits are valid only when the CD1E bit in SICDAR
is set to 1.



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