SH7713 datasheet(649/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 609 of 860

REJ09B0288-0150

17.3.10

Serial Transmit Data Register (SITDR)

SITDR is used to specify the SIOF transmit data. The setting data for this register is stored in the

transmit FIFO. SITDR is initialized by a power-on reset, software reset, or transmit reset.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16

SITDL15 to

SITDL0

All 0

Left Channel Transmit Data

Specify data to be output from the TXD_SIO pin as left

channel data. The position of the left channel data in the

transmission frame is specified by the TDLA bit in

SITDAR.

These bits are valid only when the TDLE bit in SITDAR is

set to 1.

15 to 0

SITDR15 to

SITDR0

All 0

Right Channel Transmit Data

Specify data to be output from the TXD_SIO pin as right

channel data. The position of the right channel data in the

transmission frame is specified by the TDRA bit in

SITDAR.

These bits are valid only when the TDLE bit and TLREP

bit in SITDAR are set to 1 and cleared to 0, respectively.

SH7713 Datasheet(PDF) 649 Page - Renesas Technology Corp