SH7713 datasheet(646/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 606 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RFUDR

R/W

Receive FIFO Underrun

Receive FIFO underrun means that reading of SIRDR has

occurred when the receive FIFO is empty. When a receive

underrun occurs, the value of data read from SIRDR is not

guaranteed.

This bit is valid when the RXE bit in SICTR is 1. When 1 is

written to this bit, the contents are cleared. If the issue of

interrupts by this bit is enabled, the SIOF issues an error

interrupt.

0: No receive FIFO underrun

1: Receive FIFO underrun

RFOVR

R/W

Receive FIFO Overrun

Receive FIFO overrun means that writing has occurred

when the receive FIFO is full. When a receive overrun

occurs, the SIOF indicates the overrun, and receive data is

lost.

This bit is valid when the RXE bit in SICTR is 1. When 1 is

written to this bit, the contents are cleared. If the issue of

interrupts by this bit is enabled, the SIOF issues an error

interrupt.

0: No receive FIFO overrun

1: Receive FIFO overrun

SH7713 Datasheet(PDF) 646 Page - Renesas Technology Corp