SH7713 datasheet(647/904 Pages) RENESAS

647 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 607 of 860

REJ09B0288-0150

17.3.9

SIOF Interrupt Enable Register (SIIER)

SIIER is a used to enable the issue of SIOF interrupts. When each of the bits of this register is set

to 1, and the corresponding bit of the SISTR is set to 1, the SIOF issues an interrupt. SIIER is

initialized by a power-on reset or software reset.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should always

be 0.

TCRDYE

R/W

Transmit Control Data Ready Enable

0: Disables interrupts due to transmit control data ready

1: Enables interrupts due to transmit control data ready

(control interrupt)

TFEMPE

R/W

Transmit FIFO Empty Enable

0: Disables interrupts due to transmit FIFO empty

1: Enables interrupts due to transmit FIFO empty (control

interrupt)

TDREQE

R/W

Transmit Data Transfer Request Enable

0: Disables interrupts due to transmit data transfer requests

1: Enables interrupts due to transmit data transfer requests

(transmit interrupt)



Reserved

This bit is always read as 0. The write value should always

be 0.

RCRDYE

R/W

Receive Control Data Ready Enable

0: Disables interrupts due to receive control data ready

1: Enables interrupts due to receive control data ready

(control interrupt)

RFFULE

R/W

Receive FIFO Full Enable

0: Disables interrupts due to receive FIFO full

1: Enables interrupts due to receive FIFO full (control

interrupt)

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