SH7713 datasheet(643/904 Pages) RENESAS

643 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 603 of 860

REJ09B0288-0150

17.3.8

SIOF Status Register (SISTR)

SISTR shows the SIOF state. Each of the bits of this register becomes an SIOF interrupt source

when the corresponding bit in SIIER is set to 1. SISTR is initialized by a power-on reset or

software reset.

Bit

Bit Name

Initial

Value

R/W

Description

—

Reserved

This bit is always read as 0. The write value should always be

TCRDY

Transmit Control Data Ready

This bit indicates a state of the SIOF. If SITCR is written, the

SIOF clears this bit. This bit is valid when the TXE bit in SICTR

is set to 1. If the issue of interrupts by this bit is enabled, the

SIOF issues a control interrupt. If SITCR is written when this

bit is cleared to 0, SITCR is over-written and the previous

contents of SITCR are not output from the TXD_SIO pin.

0: Indicates that a write to SITCR is disabled

1: Indicates that a write to SITCR is enabled

Note: When using this bit, see 2 in section 17.5, Usage Notes.

TFEMP

Transmit FIFO Empty

This bit indicates a state; if SITDR is written, the SIOF clears

this bit. This bit is valid when the TXE bit in SICTR is 1. If the

issue of interrupts by this bit is enabled, the SIOF issues a

control interrupt.

0: Indicates that transmit FIFO is not empty

1: Indicates that transmit FIFO is empty

TDREQ

Transmit Data Transfer Request

A transmit data transfer request is issued when the empty

space in the transmit FIFO exceeds the size specified by the

TFWM bit in SIFCTR. This bit is valid when the TXE bit in

SICTR is 1. This bit indicates a state of the SIOF. If the size of

empty space in the transmit FIFO is less than the size

specified by the TFWM bit in SIFCTR, the SIOF clears this bit.

If the issue of interrupts by this bit is enabled, the SIOF issues

a transmit interrupt.

0: No transfer request

1: Transfer request

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