SH7713 datasheet(641/904 Pages) RENESAS

641 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 601 of 860

REJ09B0288-0150

17.3.7

SIOF FIFO Control Register (SIFCTR)

SIFCTR is used to indicate the area available for the transmit/receive FIFO transfer. SIFCTR is

initialized by a power-on reset or software reset.

Bit

Bit Name

Initial

Value

R/W

Description

TFWM2

TFWM1

TFWM0

R/W

Transmit FIFO Watermark

A transfer request to the transmit FIFO is issued by the TDREQ

bit in SISTR. The transmit FIFO is always used as 16 stages of

FIFO regardless of these bit settings.

000: Issue a transfer request when 16 stages of transmit FIFO

are empty.

001: Reserved (setting prohibited)

010: Reserved (setting prohibited)

011: Reserved (setting prohibited)

100: Issue a transfer request when 12 or more stages of

transmit FIFO are empty.

101: Issue a transfer request when 8 or more stages of

transmit FIFO are empty.

110: Issue a transfer request when 4 or more stages of

transmit FIFO are empty.

111: Issue a transfer request when 1 or more stages of

transmit FIFO are empty.

TFUA4

TFUA3

TFUA2

TFUA1

TFUA0

Transmit FIFO Usable Area

Indicate the number of words that can be transferred by the

CPU or DMAC as B

′00000 to B′10000.

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