SH7713 datasheet(642/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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642 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 602 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RFWM2

RFWM1

RFWM0

R/W

Receive FIFO Watermark

A transfer request to the receive FIFO is issued by the RDREQ

bit in SISTR. The receive FIFO is always used as 16 stages of

FIFO regardless of these bit settings.

000: Issue a transfer request when 1 stage or more of receive

FIFO are valid.

001: Reserved (setting prohibited)

010: Reserved (setting prohibited)

011: Reserved (setting prohibited)

100: Issue a transfer request when 4 or more stages of receive

FIFO are valid.

101: Issue a transfer request when 8 or more stages of receive

FIFO are valid.

110: Issue a transfer request when 12 or more stages of

receive FIFO are valid.

111: Issue a transfer request when 16 stages of receive FIFO

are valid.

RFUA4

RFUA3

RFUA2

RFUA1

RFUA0

Receive FIFO Usable Area

Indicate the number of words that can be transferred by the

CPU or DMAC as B

′00000 to B′10000.

SH7713 Datasheet(PDF) 642 Page - Renesas Technology Corp