SH7713 datasheet(638/904 Pages) RENESAS

638 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 598 of 860

REJ09B0288-0150

17.3.6

SIOF Control Register (SICTR)

SICTR is used to set the SIOF operating state. SICTR is initialized by a power-on reset or

software reset.

Bit

Bit Name

Initial

Value

R/W

Description

SCKE

R/W

Serial Clock Output Enable

This bit is valid in master mode. If this bit is set to 1, the

SIOF initializes the baud rate generator and initiates the

operation. At the same time, the SIOF outputs the clock

generated in the baud rate generator to the SCK_SIO pin.

0: Disables the SCK_SIO output (outputs 0)

1: Enables the SCK_SIO output

FSE

R/W

Frame Synchronous Signal Output Enable

This bit is valid in master mode. If this bit is set to 1, the

SIOF initializes the frame counter and initiates the

operation.

0: Disables the SIOFSYNC output (outputs 0)

1: Enables the SIOFSYNC output

13 to 10

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TXE

R/W

Transmission Enable

This bit setting becomes valid at the start of the next frame

(at the rising edge of the SIOFSYNC signal) and when

valid data is stored in the transmit FIFO. When the 1

setting for this bit becomes valid, the SIOF issues a

transmission transfer request according to the setting of

the TFWM bit in SIFCTR. When transmit data is stored in

the transmit FIFO, transmission of data from the TXD_SIO

pin begins. This bit is initialized by a transmit reset.

0: Disables data transmission from TXD_SIO (outputs 1)

1: Enables data transmission from TXD_SIO

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