SH7713 datasheet(635/904 Pages) RENESAS

635 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 595 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

TLREP

R/W

Transmit Left Channel Repeat

This bit setting is valid when the TDRE bit is set to 1.

When this bit is set to 1, settings of bits SITDR15 to

SITDR0 in SITDR are ignored.

0: Transmits data specified in the SITDR bit in SITDR as

right channel data.

1: Repeatedly transmits data specified in the SITDL bit in

SITDR as right channel data

—

Reserved

These bits are always read as 0. The write value should

always be 0.

TDRA3

TDRA2

TDRA1

TDRA0

R/W

Transmit Right Channel Data Assigns

Specify the position of right-channel data in transmit frame

as B

′0000 to B′1110. Transmit data for the right channel is

specified in bits SITDR15 to SITDR0 in SITDR.

Note: If the TDRA3 to TDRA0 bits are set to B

′1111,

operation is not guaranteed.

17.3.4

Serial Receive Data Assign Register (SIRDAR)

SIRDAR is used to specify the position of the receive data in a frame. SIRDAR is initialized by a

power-on reset or software reset.

Bit

Bit Name

Initial

Value

R/W

Description

RDLE

R/W

Receive Left Channel Data Enable

0: Disables left channel data reception

1: Enables left channel data reception

14 to 12

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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