SH7713 datasheet(631/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

631 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 591 of 860

REJ09B0288-0150

17.3.1

SIOF Mode Register (SIMDR)

SIMDR is a register that sets the SIOF0/1 operating mode. SIMDR is initialized by a power-on

reset or manual reset.

Bit

Bit Name

Initial

Value

R/W

Description

TRMD1

TRMD0

R/W

Transfer Mode

Selects transfer mode.

00: Slave mode 1

01: Slave mode 2

10: Master mode 1

11: Master mode 2

Note: For the operation in each mode, see section 17.4.3,

Transfer Data Format.



Reserved

This bit is always read as 0. The write value should always

be 0.

REDG

R/W

Receive Data Sampling Edge

The TXD_SIO signal is transmitted at the opposite edge

where the RXD_SIO signal is sampled (see figure 17.4).

0: RXD_SIO is sampled at the falling edge of SCK_SIO

1: RXD_SIO is sampled at the rising edge of SCK_SIO

Note: This bit is valid in master mode 1 and master mode

SH7713 Datasheet(PDF) 631 Page - Renesas Technology Corp