SH7713 datasheet(632/904 Pages) RENESAS

632 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 592 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

FL3

FL2

FL1

FL0

R/W

Frame Length

00xx: Slot length is 8 bits and frame length is 8 bits

0100: Slot length is 8 bits and frame length is 16 bits

0101: Slot length is 8 bits and frame length is 32 bits

0110: Slot length is 8 bits and frame length is 64 bits

0111: Slot length is 8 bits and frame length is 128 bits

10xx: Slot length is 16 bits and frame length is 16 bits

1100: Slot length is 16 bits and frame length is 32 bits

1101: Slot length is 16 bits and frame length is 64 bits

1110: Slot length is 16 bits and frame length is 128 bits

1111: Slot length is 16 bits and frame length is 256 bits

Notes: 1. When slot length is specified as 8 bits, control

data cannot be transmitted or received.

2. When LSB is first transmitted or received,

control data cannot be transmitted or received.

x: Don't care

TXDIZ

R/W

High-Impedance Output when Transmission is Invalid

Specifies high-impedance output when transmission is

invalid.

0: High output (1 output) when invalid

1: High-impedance output when invalid

Note: Invalid means when disabled, and when a slot that

is not assigned as transmit data or control data is

being transmitted.

LSBF

R/W

LSB-First Transmission/Reception

Selects the bit order of a transmit/receive frame.

0: MSB-first

1: LSB-first

RCIM

R/W

Receive Control Data Interrupt Mode

Selects the set timing of the RCRDY bit in SISTR.

0: Sets the RCRDY bit in SISTR when the contents of

SIRCR change.

1: Sets the RCRDY bit in SISTR each time when SIRCR

receives control data.

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