SH7713 datasheet(627/904 Pages) RENESAS

627 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

SCIS3F0C_000020020900

Rev.1.50 Aug. 30, 2006 Page 587 of 860

REJ09B0288-0150

Section 17 Serial I/O with FIFO (SIOF)

This LSI includes a two-channel clocked synchronous serial I/O module with FIFO (SIOF) which

can be directly connected to the audio CODEC. The functions of the SIOF0 and SIOF1 are

common.

17.1

Features

The features of the SIOF are described below.

• Serial transfer

Sixteen-stage 32-bit FIFOs (transmission/reception independently)

Supports 8-bit data/16-bit data/16-bit stereo audio input/output

MSB or LSB first for data transmission/reception

Supports a maximum of 48-kHz sampling rate

Synchronization by either frame synchronization pulse or left/right channel switch

Supports CODEC control data interface

Connectable to every A-Law or

µ-Law CODEC linear audio chip manufactured by any

company

Supports both master and slave modes

• Serial clock

An external pin input or internal clock (P_CLK) can be selected as the clock source.

• Interrupts

Following four interrupts can be requested independently.

Transmission interrupt

Reception interrupt

Error interrupt

Control interrupt

• DMA transfer

Supports DMA transfer by a transfer request for transmission/reception

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