SH7713 datasheet(624/904 Pages) RENESAS

624 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 584 of 860

REJ09B0288-0150

Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state the input from the RxD pin consists of

all 0s, so the FER flag is set and the parity error flag (PER) may also be set.

Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive

operation continues.

Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous

mode, the SCIF operates on a base clock with a frequency of 16 times the transfer rate.

In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the

base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is

shown in figure 16.19.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5

Base clock

16 clocks

8 clocks

–7.5 clocks

+7.5 clocks

Start bit

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).

M = 0.5 –

– (L – 0.5)F –

(1 + F)

× 100%

D – 0.5

..................... (1)

Receive margin (%)

Ratio of clock frequency to bit rate (N = 16)

Clock duty cycle (D = 0 to 1.0)

Frame length (L = 9 to 12)

Absolute deviation of clock frequency

SH7713 Datasheet(PDF) 624 Page - Renesas Technology Corp