SH7713 datasheet(648/904 Pages) RENESAS

648 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 608 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RDREQE

R/W

Receive Data Transfer Request Enable

0: Disables interrupts due to receive data transfer requests

1: Enables interrupts due to receive data transfer requests

(receive interrupt)

7 to 5

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

FSERRE

R/W

Frame Synchronization Error Enable

0: Disables interrupts due to frame synchronization error

1: Enables interrupts due to frame synchronization error

(error interrupt)

TFOVRE

R/W

Transmit FIFO Overrun Enable

0: Disables interrupts due to transmit FIFO overrun

1: Enables interrupts due to transmit FIFO overrun (error

interrupt)

TFUDRE

R/W

Transmit FIFO Underrun Enable

0: Disables interrupts due to transmit FIFO underrun

1: Enables interrupts due to transmit FIFO underrun (error

interrupt)

RFUDRE

R/W

Receive FIFO Underrun Enable

0: Disables interrupts due to receive FIFO underrun

1: Enables interrupts due to receive FIFO underrun (error

interrupt)

RFOVRE

R/W

Receive FIFO Overrun Enable

0: Disables interrupts due to receive FIFO overrun

1: Enables interrupts due to receive FIFO overrun (error

interrupt)

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