SH7713 datasheet(685/904 Pages) RENESAS

685 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 645 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

ICD

R/W

Illegal Carrier Detection

Indicates that the PHY-LSI has detected an illegal

carrier on the line. If a change in the signal input from

the PHY-LSI occurs before the software recognition

period, the correct information may not be obtained.

Refer to the timing specification for the PHY-LSI used.

0: PHY-LSI has not detected an illegal carrier on the

line

1: PHY-LSI has detected an illegal carrier on the line

18.3.4

EtherC Interrupt Permission Register (ECSIPR)

ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources

indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

LCHNGIP

R/W

LINK Signal Changed Interrupt Enable

0: Interrupt notification by the LCHNG bit is disabled

1: Interrupt notification by the LCHNG bit is enabled

MPDIP

R/W

Magic Packet Detection Interrupt Enable

0: Interrupt notification by the MPD bit is disabled

1: Interrupt notification by the MPD bit is enabled

ICDIP

R/W

Illegal Carrier Detection Interrupt Enable

0: Interrupt notification by the ICD bit is disabled

1: Interrupt notification by the ICD bit is enabled

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