SH7713 datasheet(690/904 Pages) RENESAS

690 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 650 of 860

REJ09B0288-0150

18.3.11

Delayed Collision Detect Counter Register (CDCR)

CDCR is a 32-bit counter that indicates the number of all delayed collisions that accured on the

line after the start of data transmission. When the value in this register reaches H'FFFFFFFF,

count-up is halted. The counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 COSDC31

COSDC0

All 0

R/W

Delayed Collision Detect Count

These bits indicate the number of all delayed collisions

after the start of data transmission.

18.3.12

Lost Carrier Counter Register (LCCR)

LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data

transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The

counter value is cleared to 0 by writing to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 LCC31 to

LCC0

All 0

R/W

Lost Carrier Count

These bits indicate the number of times the carrier was

lost during data transmission.

18.3.13

Carrier Not Detect Counter Register (CNDCR)

CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected

while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count

is halted. The counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 CNDC31

to CNDC0

All 0

R/W

Carrier Not Detect Count

These bits indicate the number of times the carrier

was not detected.

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