SH7713 datasheet(691/904 Pages) RENESAS

691 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 651 of 860

REJ09B0288-0150

18.3.14

CRC Error Frame Receive Counter Register (CEFCR)

CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was

received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter

value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 CEFC31 to

CEFC0

All 0

R/W

CRC Error Frame Count

These bits indicate the count of CRC error frames

received.

18.3.15

Frame Receive Error Counter Register (FRECR)

FRECR is a 32-bit counter that indicates the number of frames for which a receive error was

indicated by the RX-ER input pin from the PHY-LSI. FRECR is incremented each time the RX-

ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted.

The counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 FREC31 to

FREC0

All 0

R/W

Frame Receive Error Count

These bits indicate the count of errors during frame

reception.

18.3.16

Too-Short Frame Receive Counter Register (TSFRCR)

TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have

been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The

counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 TSFC31 to

TSFC0

All 0

R/W

Too-Short Frame Receive Count

These bits indicate the count of frames received with a

length of less than 64 bytes.

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