SH7713 datasheet(710/904 Pages) RENESAS

710 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 670 of 860

REJ09B0288-0150

Transmit

buffer

Receive

buffer

External bus

interface

Internal bus

Transmit

descriptor

Receive

descriptor

External memory

EtherC

Transmit

FIFO

Receive

FIFO

Internal

bus

interface

Descriptor

Information

Receive DMAC

Descriptor

Information

Transmit DMAC

E-DMAC

This LSI

Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers

19.2

The E-DMAC has the following registers. For addresses and access sizes of these registers, see

section 23, List of Registers.

• E-DMAC mode register (EDMR)

• E-DMAC transmit request register (EDTRR)

• E-DMAC receive request register (EDRRR)

• Transmit descriptor list address register (TDLAR)

• Receive descriptor list address register (RDLAR)

• EtherC/E-DMAC status register (EESR)

• EtherC/E-DMAC status interrupt permission register (EESIPR)

• Transmit/receive status copy enable register (TRSCER)

• Receive missed-frame counter register (RMFCR)

• Transmit FIFO threshold register (TFTR)

• FIFO depth register (FDR)

• Receiving method control register (RMCR)

• E-DMAC operation control register (EDOCR)

• Receive buffer write address register (RBWAR)

• Receive descriptor fetch address register (RDFAR)

• Transmit buffer read address register (TBRAR)

• Transmit descriptor fetch address register (TDFAR)

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