SH7713 datasheet(711/904 Pages) RENESAS

711 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 671 of 860

REJ09B0288-0150

• Overflow alert FIFO threshold register (FCFTR)

• Transmit interrupt register (TRIMD)

19.2.1

E-DMAC Mode Register (EDMR)

EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and transmit/receive

descriptor length. This register is to be set before the TR bit in EDTRR or the RR bit in EDRRR is

set to 1. If a software reset is executed with this register during data transmission, abnormal data

may be transmitted on the line. Execute a software reset with this register before specifying

transmit/receive descriptor length and modifying the settings of TDLAR, RDLAR, and so forth,

the setting of ECMR (EtherC mode register), and the settings of registers related to E-DMAC and

EtherC operation. The time required for completion of EtherC and E-DMAC initialization from a

software reset with this register is 64 cycles of the internal bus clock B

φ. Therefore, registers of

the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock B

φ has

elapsed.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DL1

DL0

R/W

Descriptor Length

These bits specify the descriptor length. (See section

19.3.1, Descriptors and Descriptor List.)

00: 16 bytes

01: 32 bytes

10: 64 bytes

11: Reserved (setting prohibited)

3 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7713 Datasheet(PDF) 711 Page - Renesas Technology Corp

SH7713 Datasheet(HTML) 711 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL