SH7713 datasheet(712/904 Pages) RENESAS

712 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 672 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

SWR

R/W

Software Reset

By writing 1 to this bit, the registers of the E-DMAC

other than TDLAR, RDLAR, and RMFCR and the

registers of EtherC other than TSU-related registers

can be initialized. (The registers whose names start

with TSU_ are not initialized.) The SWR bit in EDMR

initializes the EDMAC and MAC registers in the

EtherC. While a software reset is issued (64 cycles of

the internal bus clock B

φ), accesses to the all

Ethernet-related registers are prohibited.

Software reset period (example):

When B

φ = 100 MHz: 0.64 µS

When B

φ = 66 MHz: 0.97 µS

When B

φ = 50 MHz: 1.28 µS

When B

φ = 33 MHz: 1.94 µS

This bit is always read as 0.

1: EtherC and E-DMAC are reset (when writing)

19.2.2

E-DMAC Transmit Request Register (EDTRR)

EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After

writing 1 to the TR bit in this register, the E-DMAC reads the transmit descriptor at the address

specified by TDLAR. If the TACT bit of this descriptor is set to 1 (valid), transmit DMA transfer

by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is completed,

the E-DMAC reads the next transmit descriptor. If the TACT bit of that descriptor is set to 1

(valid), the E-DMAC continues transmit DMA operation. If the TACT bit of a transmit descriptor

is cleared to 0 (invalid), the E-DMAC clears the TR bit and stops transmit DMAC operation.

For details of writing to the TR bit, see section 19.4.1, Using of EDTRR and EDRRR.

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