SH7713 datasheet(716/904 Pages) RENESAS

716 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 676 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

TWB

R/W

Write-Back Complete

Indicates that write-back from the E-DMAC to the

corresponding descriptor has completed. This

operation is enabled when the TIS bit in TRIMD is set

to 1.

0: Write-back has not completed, or no transmission

directive

1: Write-back has completed

29 to 27



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TABT

R/W

Transmit Abort Detection

Indicates that the EtherC aborts transmitting a frame

because of failures during transmitting the frame.

0: Frame transmission has not been aborted or no

transmit directive

1: Frame transmit has been aborted

RABT

R/W

Receive Abort Detection

Indicates that the EtherC aborts receiving a frame

because of failures during receiving the frame.

0: Frame reception has not been aborted or no

receive directive

1: Frame receive has been aborted

RFCOF

R/W

Receive Frame Counter Overflow

Indicates that the receive FIFO frame counter has

overflowed.

0: Receive frame counter has not overflowed

1: Receive frame counter overflows

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