SH7713 datasheet(719/904 Pages) RENESAS

719 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 679 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RDE

R/W

Receive Descriptor Empty

Indicates that the RACT bit of a receive descriptor

read by the E-DMAC for receive DMA is cleared to 0

(invalid).

When receive descriptor empty (RDE = 1) occurs,

reception can be resumed by setting the RACT bit

(cleared to 0) of the receive descriptor to 1 and

writing 1 to the RR bit in EDRRR.

0: Receive descriptor active bit RACT = 1 detected

1: Receive descriptor active bit RACT = 0 detected

RFOF

R/W

Receive FIFO Overflow

Indicates that the receive FIFO has overflowed during

frame reception.

0: Overflow has not occurred

1: Overflow has occurred

15 to 12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CND

R/W

Carrier Not Detect

Indicates the carrier detection status during preamble

transmission.

0: A carrier is detected when transmission starts

1: A carrier is not detected

DLC

R/W

Detect Loss of Carrier

Indicates that loss of the carrier has been detected

during frame transmission.

0: Loss of carrier not detected

1: Loss of carrier detected

R/W

Delayed Collision Detect

Indicates that a delayed collision has been detected

during frame transmission.

0: Delayed collision not detected

1: Delayed collision detected

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