SH7713 datasheet(717/904 Pages) RENESAS

717 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 677 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

ADE

R/W

Address Error

Indicates that the memory address that the E-DMAC

tried to transfer is found illegal.

0: Illegal memory address not detected (normal

operation)

1: Illegal memory address detected

Note:

When an address error is detected, the

E-DMAC halts transmitting/receiving. To

resume the operation, execute a software

reset with the SWR bit in EDMR.

ECI

EtherC Status Register Interrupt Source

This bit is a read-only bit. When the source of an

ECSR interrupt in the EtherC is cleared, this bit is

also cleared.

0: EtherC status interrupt source has not been

detected

1: EtherC status interrupt source has been detected

R/W

Frame Transmit Complete

Indicates that all the data specified by the transmit

descriptor has been transmitted from the EtherC. This

bit is set to 1, assuming the completion of

transmission, when transmission of one frame is

completed in single-frame/single-descriptor operation

or when the last data of a frame has been transmitted

and the transmit descriptor valid bit (TACT) of the

next descriptor is not set in for the processing of

multi-buffer frame based on single-frame/multi-

descriptor operation. After frame transmission, the E-

DMAC writes the transmission status back to the

relevant descriptor.

0: Transfer not complete, or no transfer directive

1: Transfer complete

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