SH7713 datasheet(737/904 Pages) RENESAS

737 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 697 of 860

REJ09B0288-0150

(a)

Transmit Descriptor 0 (TD0)

Before the TR bit in EDTRR is set to 1, the user sets the descriptor valid/invalid bit and sets other

descriptor configuration. After completion of Ethernet frame transmission, the E-DMAC disables

the descriptor valid/invalid bit and writes status information. This operation is referred to as write-

back.

When using TD0, the user should write desired values to bits 31 to 28 according to the descriptor

configuration. Write 0 to bits 27 to 0.

Bit

Bit Name

Initial

Value

R/W

Description

TACT

R/W

Transmit Descriptor Valid/Invalid

Indicates whether the corresponding descriptor is

valid or invalid. To make this bit valid, store transmit

data in a transmit buffer (user-specified transmit data

storage destination) beforehand, then write 1 to this

bit. The E-DMAC clears this bit to 0 upon completion

of data transfer.

0: Indicates that the transmit descriptor is invalid

Indicates the initial setting state, the state after 0 is

written, or (in case the user writes 1 to this bit) that

this bit is cleared to 0 because of completion of the

processing of the E-DMAC data transfer.

If this state is recognized when the E-DMAC reads

a descriptor, the E-DMAC clears the TR bit in

EDTRR to 0, and halts transfer operation related to

transmission by the E-DMAC.

1: Indicates that the transmit descriptor is valid

After the user writes 1 to this bit, this bit indicates

that data is not transferred yet or data is being

transferred.

When there is a descriptor row (descriptor list)

consisting of multiple continuous descriptors, the

E-DMAC can continue operation when this bit of

the next descriptor is valid.

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