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SH7713 Datasheet(PDF) 733 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 733 Page - Renesas Technology Corp |
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733 / 904 page ![]() Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev.1.50 Aug. 30, 2006 Page 693 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 31 to 19 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 18 17 16 RFF2 RFF1 RFF0 1 1 1 R/W R/W R/W Receive FIFO Overflow Alert Signal Output Threshold 000: When one receive frame has been stored in the receive FIFO 001: When two receive frames have been stored in the receive FIFO : : 110: When seven receive frames have been stored in the receive FIFO 111: When eight receive frames have been stored in the receive FIFO 15 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 RFD2 RFD1 RFD0 1 1 1 R/W R/W R/W Receive FIFO Overflow Alert Signal Output Threshold 000: When (256 − 32) bytes of data is stored in the receive FIFO 001: When (512 − 32) bytes of data is stored in the receive FIFO : : 110: When (1792 − 32) bytes of data is stored in the receive FIFO 111: When (2048 − 64) bytes of data is stored in the receive FIFO |
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