SH7713 datasheet(734/904 Pages) RENESAS

734 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 694 of 860

REJ09B0288-0150

19.2.19

Transmit Interrupt Register (TRIMD)

TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back

completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TIS

R/W

Transmit Interrupt Setting

0: Write-backed completion for each frame using the

TWB bit in EESR is notified

1: Write-back completion for each frame is not

notified

19.3

Operation

Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of

transmit/receive data between a Ethernet frame transmission/reception data storage destination of

user- specified (accessible memory space: transmit buffer/receive buffer) and the transmit/receive

FIFO in the E-DMAC. (The user cannot read and write data in the transmit/receive FIFO directly

via the CPU).

To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive

data storage address and so forth, referred to as a descriptor, is required. Before Ethernet frame

transmission/reception, the E-DMAC reads descriptor information, then reads transmit data from

the transmit buffer or writes receive data to the receive buffer according to the read descriptor

information. By arranging multiple descriptors as a descriptor row (list) (to be placed in a

readable/writable memory space), multiple Ethernet frames can be transmitted or received

continuously.

SH7713 Datasheet(PDF) 734 Page - Renesas Technology Corp