SH7713 datasheet(730/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 690 of 860

REJ09B0288-0150

19.2.13

E-DMAC Operation Control Register (EDOCR)

EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC

operation.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

FEC

R/W

FIFO Error Control

Specifies E-DMAC operation when transmit FIFO

underflow or receive FIFO overflow occurs.

0: E-DMAC operation continues when underflow or

overflow occurs

1: E-DMAC operation halts when underflow or

overflow occurs

AEC

R/W

Address Error Control

Indicates detection of an illegal memory address in

an attempted E-DMAC transfer.

0: Illegal memory address not detected (normal

operation)

1: Indicates that E-DMAC operation is halted because

an illegal memory address is detected. When 0 is

written to this bit, the E-DMAC resumes operation

1 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7713 Datasheet(PDF) 730 Page - Renesas Technology Corp

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