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SH7713 Datasheet(PDF) 727 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 727 Page - Renesas Technology Corp |
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727 / 904 page  Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev.1.50 Aug. 30, 2006 Page 687 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 31 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TFT10 to TFT0 All 0 R/W Transmit FIFO threshold When setting a transmit FIFO, the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR. H ′00: Store and forward modes H ′01 to H′0C: Setting prohibited H ′0D: 52 bytes H ′0E: 56 bytes : : H ′1F: 124 bytes H ′20: 128 bytes : : H ′3F: 252 bytes H ′40: 256 bytes : : H ′7F: 508 bytes H ′80: 512 bytes : : H ′FF: 1020 bytes H ′100: 1024 bytes : : H ′1FF: 2044 bytes H ′200: 2048 bytes Note: When starting transmission before one frame of data write has completed, take care the generation of the underflow. |
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