SH7713 datasheet(728/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 688 of 860

REJ09B0288-0150

19.2.11

FIFO Depth Register (FDR)

FDR is a 32-bit readable/writable register that specifies the size of the transmit and receive FIFOs.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 8

TFD2 to

TFD0

All 1

R/W

Transmit FIFO Size

Specifies 256 bytes to 2 kbytes in 256-byte units as

the size of the transmit FIFO. The setting must not be

changed after transmission/reception has started.

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

2 to 0

RFD2 to

RFD0

All 1

R/W

Receive FIFO Size

Specifies 256 bytes to 2 kbytes in 256-byte units as

the size of the receive FIFO. The setting must not be

changed after transmission/reception has started.

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