SH7713 datasheet(724/904 Pages) RENESAS

724 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 684 of 860

REJ09B0288-0150

19.2.8

Transmit/Receive Status Copy Enable Register (TRSCER)

TRSCER indicates whether multicast address frame receive status information reported by bit 7 in

EESR is reflected in the RFE bit in the corresponding descriptor (for details of descriptor

descriptions, see section 19.3.1, Descriptors and Descriptor List).

The RMAFCE bit in this register corresponds to bit 7 in EESR. When the RMAFCE bit is cleared

to 0, the receive status (bit 7 in EESR) is reflected in the RFE bit in the receive descriptor. When

this bit is set to 1, the status is not reflected in the descriptor even if the corresponding source

occurs. The RMAFCE bit is cleared to 0 after a power-on reset and manual reset.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

RMAFCE

R/W

RMAF Bit Copy Directive

0: Reflects the RMAF bit status in the RFE bit of the

receive descriptor

1: Occurrence of the corresponding source is not

reflected in the RFE bit of the receive descriptor

6 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7713 Datasheet(PDF) 724 Page - Renesas Technology Corp