SH7713 datasheet(731/904 Pages) RENESAS

731 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 691 of 860

REJ09B0288-0150

19.2.14

Receive Buffer Write Address Register (RBWAR)

RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes

data to the receiving buffer. Which addresses in the receiving buffer are processed by the E-

DMAC can be recognized by monitoring addresses displayed in this register. The address that the

E-DMAC is actually processing may be different from the value read from this register.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

RBWA31 to

RBWA0

All 0

Receiving-Buffer Write Address

These bits can only be read. Writing is prohibited.

19.2.15

Receive Descriptor Fetch Address Register (RDFAR)

RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor

information from the receiving descriptor. Which receiving descriptor information is used for

processing by the E-DMAC can be recognized by monitoring addresses displayed in this register.

The address from which the E-DMAC is actually fetching a descriptor may be different from the

value read from this register.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

RDFA31 to

RDFA0

All 0

Receiving-Descriptor Fetch Address

These bits can only be read. Writing is prohibited.

19.2.16

Transmit Buffer Read Address Register (TBRAR)

TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the

transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC

can be recognized by monitoring addresses displayed in this register. The address from which the

E-DMAC is actually reading in the buffer may be different from the value read from this register.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

TBRA31 to

TBRA0

All 0

Transmission-Buffer Read Address

These bits can only be read. Writing is prohibited.

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