SH7713 datasheet(288/904 Pages) RENESAS

288 / 904 page

Section 8 Interrupt Controller (INTC)

Rev.1.50 Aug. 30, 2006 Page 248 of 860

REJ09B0288-0150

As shown in table 8.5, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit

groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)

are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is

requested); H'F means priority level 15 (the highest level).

8.4.2

Interrupt Control Register 0 (ICR0)

ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and

indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a

power-on reset or manual reset, but is not initialized in standby mode.

Bit

Bit Name

Initial Value

R/W

Description

NMIL

0/1*

NMI Input Level

Sets the level of the signal input at the NMI pin.

This bit can be read from to determine the NMI

pin level. This bit cannot be modified.

0 : NMI input level is low

1 : NMI input level is high



Reserved

These bits are always read as 0. The write value

should always be 0.

NMIE

R/W

NMI Edge Select

Selects whether the falling or rising edge of the

interrupt request signal at the NMI pin is

detected.

0 : Interrupt request is detected on falling edge

of NMI pin input

1 : Interrupt request is detected on rising edge of

NMI pin input

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