SH7713 datasheet(289/904 Pages) RENESAS

289 / 904 page

Section 8 Interrupt Controller (INTC)

Rev.1.50 Aug. 30, 2006 Page 249 of 860

REJ09B0288-0150

Bit

Bit Name

Initial Value

R/W

Description



Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

when NMI input is high, 0 when NMI input is low.

8.4.3

Interrupt Control Register 1 (ICR1)

ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to

IRQ5 individually: rising edge, falling edge, high level, or low level. This register is initialized to

′4000 by a power-on reset or manual reset, but is not initialized in standby mode.

Bit

Bit Name

Initial Value

R/W

Description

MAI

R/W

All Interrupt Mask

When this bit is set to 1, all interrupt requests are

masked while low level is input to the NMI pin. In

standby mode, an NMI interrupt is masked.

0: When the NMI pin is low, all interrupt requests

are not masked

1: When the NMI pin is low, all interrupt requests

are masked

IRQLVL

R/W

Interrupt Request Level Detection

Enables or disables the use of pins IRQ3 to IRQ0

as four independent interrupt pins. The IRQ4 and

IRQ5 pins are not affected.

0 : Use of pins IRQ3 to IRQ0 as four independent

interrupt pins enabled

1 : Use of pins

IRL3 to IRL0 as encoded 15 level

interrupt pins

SH7713 Datasheet(PDF) 289 Page - Renesas Technology Corp

SH7713 Datasheet(HTML) 289 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL