SH7713 datasheet(293/904 Pages) RENESAS

293 / 904 page

Section 8 Interrupt Controller (INTC)

Rev.1.50 Aug. 30, 2006 Page 253 of 860

REJ09B0288-0150

8.4.6

Interrupt Request Register 2 (IRR2)

IRR2 is an 8-bit register that indicates whether interrupt requests from the SCIF1 are generated.

This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in

standby mode.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TXI1R

TXI1 Interrupt Request

Indicates whether the TXI1 (SCIF1) interrupt

request is generated.

0: TXI1 interrupt request is not generated

1: TXI1 interrupt request is generated

BRI1R

BRI1 Interrupt Request

Indicates whether the BRI1 (SCIF1) interrupt

request is generated.

0: BRI1 interrupt request is not generated

1: BRI1 interrupt request is generated

RXI1R

RXI1 Interrupt Request

Indicates whether the RXI1 (SCIF1) interrupt

request is generated.

0: RXI1 interrupt request is not generated

1: RXI1 interrupt request is generated

ERI1R

ERI1 Interrupt Request

Indicates whether the ERI1 (SCIF1) interrupt

request is generated.

0: ERI1 interrupt request is not generated

1: ERI1 interrupt request is generated

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