SH7713 datasheet(295/904 Pages) RENESAS

295 / 904 page

Section 8 Interrupt Controller (INTC)

Rev.1.50 Aug. 30, 2006 Page 255 of 860

REJ09B0288-0150

8.4.8

Interrupt Request Register 4 (IRR4)

IRR4 is an 8-bit register that indicates whether interrupt requests from the TMU2, TMU1, TMU0,

WDT, and REF are generated. This register is initialized to H'00 by a power-on reset or manual

reset, but is not initialized in standby mode.

Bit

Bit Name

Initial Value

R/W

Description



Reserved

This bit always read as 0. The write value

should always be 0.

TUNI2R

TUNI2 Interrupt Request

Indicates whether the TUNI2 (TMU2) interrupt

request is generated.

0: TUNI2 interrupt request is not generated

1: TUNI2 interrupt request is generated

TUNI1R

TUNI1Interrupt Request

Indicates whether the TUNI1 (TMU1) interrupt

request is generated.

0: TUNI1 interrupt request is not generated

1: TUNI1 interrupt request is generated

TUNI0R

TUNI0 Interrupt Request

Indicates whether the TUNI0 (TMU0) interrupt

request is generated.

0: TUNI0 interrupt request is not generated

1: TUNI0 interrupt request is generated

ITIR

ITI Interrupt Request

Indicates whether the ITI (WDT) interrupt

request is generated.

0: ITI interrupt request is not generated

1: ITI interrupt request is generated



Reserved

These bits are always read as 0. The write value

should always be 0.

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