SH7713 datasheet(323/904 Pages) RENESAS

323 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 283 of 860

REJ09B0288-0150

9.3.2

Break on Instruction Fetch Cycle

1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register

(BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it

breaks before or after the execution of the instruction can then be selected with the PCBA or

PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction

fetch cycle is set as a break condition, clear LSB in the break address register (BARA or

BARB) to 0. A break cannot be generated as long as this bit is set to 1.

2. An instruction set for a break before execution breaks when it is confirmed that the instruction

has been fetched and will be executed. This means this feature cannot be used on instructions

fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to

be executed). When this kind of break is set for the delay slot of a delayed branch instruction,

the break is generated prior to execution of the delayed branch instruction.

Note:

If a branch does not occur at a delay condition branch instruction, the subsequent

instruction is not recognized as a delay slot.

3. When the condition is specified to be occurred after execution, the instruction set with the

break condition is executed and then the break is generated prior to the execution of the next

instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.

When this kind of break is set for a delayed branch instruction and its delay slot, a break is not

generated until the first instruction at the branch destination.

4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is

ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle.

5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the

instruction fetch cycles on the I bus. For details, see 5 in section 9.3.1, Flow of the User Break

Operation.

9.3.3

Break on Data Access Cycle

1. If the L bus is specified as a break condition for data access break, condition comparison is

performed for the logical addresses (and data) accessed by the executed instructions, and a

break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition

comparison is performed for the physical addresses (and data) of the data access cycles that are

issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is

satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 9.3.1, Flow of

the User Break Operation.

2. The relationship between the data access cycle address and the comparison condition for each

operand size is listed in table 9.3.

SH7713 Datasheet(PDF) 323 Page - Renesas Technology Corp