SH7713 datasheet(326/904 Pages) RENESAS

326 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 286 of 860

REJ09B0288-0150

9.3.6

Value of Saved Program Counter

When a break occurs, the address of the instruction from where execution is to be resumed is

saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break

condition, the instruction at which the break should occur can be clearly determined (except for

when data is included in the break condition). If the I bus is specified as a break condition, the

instruction at which the break should occur cannot be clearly determined.

1. When instruction fetch (before instruction execution) is specified as a break condition:

The address of the instruction that matched the break condition is saved in the SPC. The

instruction that matched the condition is not executed, and the break occurs before it. However

when a delay slot instruction matches the condition, the address of the delayed branch

instruction is saved in the SPC.

2. When instruction fetch (after instruction execution) is specified as a break condition:

The address of the instruction following the instruction that matched the break condition is

saved in the SPC. The instruction that matches the condition is executed, and the break occurs

before the next instruction is executed. However when a delayed branch instruction or delay

slot matches the condition, these instructions are executed, and the branch destination address

is saved in the SPC.

3. When data access (address only) is specified as a break condition:

The address of the instruction immediately after the instruction that matched the break

condition is saved in the SPC. The instruction that matches the condition is executed, and the

break occurs before the next instruction is executed. However when a delay slot instruction

matches the condition, the branch destination address is saved in the SPC.

4. When data access (address + data) is specified as a break condition:

When a data value is added to the break conditions, the address of an instruction that is within

two instructions of the instruction that matched the break condition is saved in the SPC. At

which instruction the break occurs cannot be determined accurately.

When a delay slot instruction matches the condition, the branch destination address is saved in

the SPC. If the instruction following the instruction that matches the break condition is a

branch instruction, the break may occur after the branch instruction or delay slot has finished.

In this case, the branch destination address is saved in the SPC.

SH7713 Datasheet(PDF) 326 Page - Renesas Technology Corp