SH7713 datasheet(322/904 Pages) RENESAS

322 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 282 of 860

REJ09B0288-0150

 Several bus masters, including the CPU, DMAC and E-DMAC, are connected to the I bus.

The UBC monitors bus cycles generated by all bus masters, and determines the condition

match.

 Physical addresses are used for the I bus. Set a physical address in break address registers

(BARA and BARB). The bus cycles for logical addresses issued on the L bus by the CPU

are converted to physical addresses before being output to the I bus. (If the address

translation function is enabled, address translation by the MMU is carried out.)

 For data access cycles issued on the L bus by the CPU, if their logical addresses are not to

be cached, they are issued with the data size specified on the L bus and their addresses are

not rounded.

 For instruction fetch cycles issued on the L bus by the CPU, even though their logical

addresses are not to be cached, they are issued in longwords and their addresses are

rounded to match longword boundaries.

 If a logical address issued on the L bus by the CPU is an address to be cached and a cache

miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued

in longwords and its address is rounded to match longword boundaries. However note that

cache fill is not performed for a write miss in write through mode. In this case, the bus

cycle is issued with the data size specified on the L bus and its address is not rounded. In

write back mode, a write back cycle may be issued in addition to a read fill cycle. It is a

longword bus cycle whose address is rounded to match longword boundaries.

 I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by

the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are

defined as data access cycles.

 The DMAC and E-DMAC only issues data access cycles for I bus cycles.

 If a break condition is specified for the I bus, even when the condition matches in an I bus

cycle resulting from an instruction executed by the CPU, at which instruction the break is

to be accepted cannot be clearly defined.

6. While the block bit (BL) in the CPU status register (SR) is set to 1, no breaks can be accepted.

However, condition determination will be carried out, and if the condition matches, the

corresponding condition match flag is set to 1.

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