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SH7713 Datasheet(PDF) 318 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 318 Page - Renesas Technology Corp |
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318 / 904 page  Section 9 User Break Controller Rev.1.50 Aug. 30, 2006 Page 278 of 860 REJ09B0288-0150 9.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 12 – 1 times. When a break condition is satisfied, it decreases BETR. A break is issued when the break condition is satisfied after BETR becomes H'0001. Bit Bit Name Initial Value R/W Description 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET11 to BET0 All 0 R/W Number of Execution Times Note: When the instruction fetch cycle is specified as the break condition of the channel B, and its break condition is triggerd by the following instructions, the BETR is decrimented by the following value (not by one). Instruction Decrement value Instruction Decrement value RTE DMULS.L Rm,Rn DMULU.L Rm,Rn MAC.L @Rm+,@Rn MAC.W @Rm+,@Rn MUL.L Rm,Rn AND.B #imm,@(R0,GBR) OR.B #imm,@(R0,GBR) TAS.B @Rn TST.B #imm,@(R0,GBR) XOR.B #imm,@(R0,GBR) LDC Rm,SR LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR LDC Rm,SPC LDC Rm,R0_BANK LDC Rm,R1_BANK LDC Rm,R2_BANK LDC Rm,R3_BANK LDC Rm,R4_BANK LDC Rm,R5_BANK LDC Rm,R6_BANK LDC Rm,R7_BANK 4 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+,R0_BANK LDC.L @Rm+,R1_BANK LDC.L @Rm+,R2_BANK LDC.L @Rm+,R3_BANK LDC.L @Rm+,R4_BANK LDC.L @Rm+,R5_BANK LDC.L @Rm+,R6_BANK LDC.L @Rm+,R7_BANK LDC.L @Rn+,MOD LDC.L @Rn+,RS LDC.L @Rn+,RE LDC Rn,MOD LDC Rn,RS LDC Rn,RE BSR label BSRF Rm JSR @Rm 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 |
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