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SH7713 Datasheet(PDF) 315 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 315 Page - Renesas Technology Corp |
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315 / 904 page ![]() Section 9 User Break Controller Rev.1.50 Aug. 30, 2006 Page 275 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 19 to 16 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches 12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches |
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