SH7713 datasheet(316/904 Pages) RENESAS

316 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 276 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

PCTE

R/W

PC Trace Enable

0: Disables PC trace

1: Enables PC trace

PCBA

R/W

PC Break Select A

Selects the break timing of the instruction fetch cycle for

channel A as before or after instruction execution.

0: PC break of channel A is set before instruction

execution

1: PC break of channel A is set after instruction

execution



Reserved

These bits are always read as 0. The write value should

always be 0.

DBEB

R/W

Data Break Enable B

Selects whether or not the data bus condition is

included in the break condition of channel B.

0: No data bus condition is included in the condition of

channel B

1: The data bus condition is included in the condition of

channel B

PCBB

R/W

PC Break Select B

Selects the break timing of the instruction fetch cycle for

channel B as before or after instruction execution.

0: PC break of channel B is set before instruction

execution

1: PC break of channel B is set after instruction

execution



Reserved

These bits are always read as 0. The write value should

always be 0.

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